Hardware Reference
In-Depth Information
within that address space is presented to the MMU, it uses special circuitry to com-
pare the virtual page number contained in it to all the TLB entries at once. If a
match is found, the page frame number in that TLB entry is combined with the off-
set taken from the virtual address to form a 32-bit physical address and produce
some flags, such as protection bits. The TLB is illustrated in Fig. 6-18(b).
However, if no match is found, a
TLB miss
occurs, which initiates a hardware
''walk'' of the page tables. When the new physical-page descriptor entry is located
in the page table, it is checked to see if the page is in memory and, if so, its corres-
ponding address translation is loaded into the TLB. If the page is not in memory, a
standard page-fault action is started. Since the TLB has only a few entries, it is
quite likely to displace an existing entry in the TLB. Future accesses to the dis-
placed page will have to once again walk the page tables to get an address map-
ping. If too many pages are being touched too quickly, the TLB will thrash, and
most memory accesses will require a 200% overhead for address translation.
It is interesting to compare the Core i7 and OMAP4430 ARM CPU virtual
memory systems. The Core i7 supports pure segmentation, pure paging, and paged
segments. The OMAP4430 ARM CPU has only paging. Both the Core i7 and the
OMAP4430 use hardware to walk the page table to reload the TLB in the event of
a TLB miss. Other architectures, such as SPARC and MIPS, just give control to the
operating system on a TLB miss. These architectures define special privileged in-
structions to manipulate the TLB, such that the operating system can perform the
page-table walks and TLB loads necessary for address translation.
Although at first glance, (demand-paged) virtual memory and caching may
look unrelated, they are conceptually very similar. With virtual memory, the entire
program is kept on disk and broken up into fixed-size pages. Some subset of these
pages are in main memory. If the program mostly uses the pages in memory, there
will be few page faults and the program will run fast. With caching, the entire pro-
gram is kept in main memory and broken up into fixed-size cache blocks. Some
subset of these blocks are in the cache. If the program mostly uses the blocks in
the cache, there will be few cache misses and the program will run fast. Con-
ceptually, the two are identical, only operating at different levels in the hierarchy.
Of course, virtual memory and caching also have some differences. For one,
cache misses are handled by the hardware, whereas page faults are handled by the
operating system. Also, cache blocks are typically much smaller than pages (e.g.,
64 bytes vs. 8 KB). In addition, the mapping between virtual pages and page
frames is different, with page tables organized by indexing on the high-order bits
of the virtual address, whereas caches index on the low-order bits of the memory
address. Nevertheless, it is important to realize that these are implementation dif-
ferences. The underlying concept is very similar.
