Hardware Reference
In-Depth Information
The ARM Architecture was first introduced in 1985 by Acorn Computer. The
architecture was inspired by the research done at Berkeley in the 1980s (Patterson,
1985, and Patterson and S´quin, 1982). The original ARM architecture (called the
ARM2) was a 32-bit architecture that supported a 26-bit address space. The
OMAP4430 utilizes the ARM Cortex A9 microarchitecture, which implements the
version 7 of the ARM architecture, and that is the ISA we will describe in this
chapter. For consistency with the rest of the topic, we will refer to the OMAP4430
here, but at the ISA level, all designs based on the ARM Cortex A9 core imple-
ment the same ISA.
The OMAP4430 memory structure is clean and simple: addressable memory is
a linear array of 2
32
bytes. ARM processors are bi-endian, such that they can ac-
cess memory with big- or little- endian order. The endian is specified in a system
memory block that is read immediately after processor reset. To ensure that the
system memory block is read correctly, it must be in little-endian format, even if
the machine is to be configured for big-endian operation.
It is important that the ISA have a larger address-space limit than imple-
mentations need, because future implementations almost certainly will need to in-
crease the size of memory the processor can access. The ARM ISA's 32-bit ad-
dress space is giving many designers growing pains, since many ARM-based sys-
tems, such as smartphones, already have more than 2
32
bytes of memory. To date,
designers have worked around these problems by making the bulk of the memory
flash-drive storage, which is accessed with a disk interface that supports a larger
block-oriented address space. To address this potentially market-killing limitation,
ARM (the company) recently published the definition of the ARM version 8 ISA,
which support 64-bit address spaces.
A serious problem encountered with successful architectures has been that
their ISA limited the amount of addressable memory. In computer science, the
only error one cannot work around is not enough bits. One day your grandchildren
will ask you how computers could do anything in the old days with only 32-bit ad-
dresses and only 4 GB of real memory when the average game needs 1 TB just to
boot up.
The ARM ISA is clean, though the organization of the registers is somewhat
quirky in an attempt to simplify some instruction encodings. The architecture
maps the program counter into the integer register file (as register
R15
), as this al-
lows branches to be created with ALU operations that have
R15
as a destination
register. Experience has shown that the register organization is more trouble than it
is worth, but ye olde backwarde-compatibility rule made it well nigh impossible to
get rid of.
The ARM ISA has two groups of registers. These are the 16 32-bit gener-
al-purpose registers and the 32 32-bit floating-point registers (if the VFP coproc-
essor is supported). The general-purpose registers are called
R0
through
R15
,
