THE INSTRUCTION SET ARCHITECTURE LEVEL - Structured Computer Organization - page 353

Bits 16 8 8

AX

EAX

AH AL

BX

EBX

BH BL

CX

ECX

CH CL

DX

EDX

DH DL

ESI

EDI

EBP

ESP

CS

SS

DS

ES

FS

GS

EIP

EFLAGS

Figure 5-3. The Core i7's primary registers.

the hardware string-manipulation instructions, where ESI points to the source string
and EDI points to the destination string. The EBP register is also a pointer register.
It is typically used to point to the base of the current stack frame, the same as LV in
IJVM. When a register (like EBP ) is used to point to the base of the local stack
frame, it is usually called the frame pointer . Finally, ESP is the stack pointer.
The next group of registers, CS through GS , are segment registers. To some
extent, they are electronic trilobites, ancient fossils left over from the time the 8088
attempted to address 2 20 bytes of memory using 16-bit addresses. Suffice it to say
that when the Core i7 is set up to use a single linear 32-bit address space, they can
be safely ignored. Next is EIP , which is the program counter (Extended Instruction
Pointer). Finally, we come to EFLAGS , which is the PSW .