Hardware Reference
In-Depth Information
Memory
control
registers
MAR
To
and
from
main
memory
MDR
PC
Instruction
fetch unit
(IFU)
MBR
MBR2
SP
LV
Control signals
CPP
Enable onto B bus
TOS
Write C bus to register
OPC
Cbus
Bbus
H
Abus
6
ALU
control
N
ALU
Z
Shifter
Figure 4-29.
The data path for Mic-2.
transition to a state one lower than its current one. If the new state is 2, the IFU
starts fetching a word from memory. All of this is in hardware. The microprogram
does not have to do anything. That is why
IADD
can be reduced from four microin-
structions to three.
The Mic-2 improves some instructions more than others.
LDC W
goes from
nine microinstructions to only three, cutting its execution time by a factor of three.
