Hardware Reference
In-Depth Information
dedicated incrementer so that the main ALU is not needed to increment it to get the
next word. The IFU must monitor the C bus so that whenever
PC
is loaded, the
new
PC
value is also copied into
IMAR
. Since the new value in
PC
may not be on a
word boundary, the IFU has to fetch the necessary word and adjust the shift regis-
ter appropriately.
With the IFU, the main execution unit writes to
PC
only when the sequential
nature of the instruction byte stream must be changed. It writes on a successful
branch instruction and on
INVOKEVIRTUAL
and
IRETURN
.
Since the microprogram no longer explicitly increments
PC
as opcodes are
fetched, the IFU must keep
PC
current. It does this by sensing when a byte from
the instruction stream has been consumed, that is, when
MBR1
or
MBR2
(or the un-
signed versions) have been read. Associated with
PC
is a separate incrementer, ca-
pable of incrementing by 1 or 2, depending on how many bytes have been con-
sumed. Thus the PC always contains the address of the first byte that has not been
consumed. At the beginning of each instruction,
MBR
contains the address of the
opcode for that instruction.
Note that there are two separate incrementers and they perform different func-
tions.
PC
counts
bytes
and increments by 1 or 2.
IMAR
counts
words
and incre-
ments only by 1 (for 4 new bytes). Like
MAR
,
IMAR
is wired to the address bus
''diagonally'' with
IMAR
bit 0 connected to address line 2, and so on, to perform an
implicit conversion of word addresses to byte addresses.
As we will see shortly in detail, not having to increment
PC
in the main loop is
a big win, because the microinstruction in which
PC
is incremented often does lit-
tle else except increment
PC
. If this microinstruction can be eliminated, the execu-
tion path can be reduced. The trade-off here is more hardware for a faster ma-
chine, so our third technique for reducing path length is
Have instructions fetched from memory by a specialized functional unit.
The IFU can greatly reduce the path length of the average instruction. First, it
eliminates the main loop entirely, since the end of each instruction simply branches
directly to the next instruction. Second, it avoids tying up the ALU incrementing
PC
. Third, it reduces the path length whenever a 16-bit index or offset is calcu-
lated, because it assembles the 16-bit value and supplies it directly to the ALU as a
32-bit value, avoiding the need for assembly in
H
. Figure 4-29 shows the Mic-2,
an enhanced version of the Mic-1 where the IFU of Fig. 4-27 has been added. The
microcode for the enhanced machine is shown in Fig. 4-30.
As an example of how the Mic-2 works, look at
IADD
. It fetches the second
word on the stack and does the addition as before, only now it does not have to go
to
Main1
when it is done to increment
PC
and dispatch to the next microinstruction.
When the IFU sees that
MBR1
has been referenced in
iadd3
, its internal shift regis-
ter pushes everything to the right and reloads
MBR1
and
MBR2
. It also makes a
