THE MICROARCHITECTURE LEVEL - Structured Computer Organization - page 249

We said that the subcycles can be best thought of as being implicit . By this we
mean there are no clock pulses or other explicit signals to tell the ALU when to op-
erate or tell the results to enter the C bus. In reality, the ALU and shifter run all the
time. However, their inputs are garbage until a time Δ w +Δ x after the falling edge

of the clock. Likewise, their outputs are garbage until y has elapsed

after the falling edge of the clock. The only explicit signals that drive the data path
are the falling edge of the clock, which starts the data path cycle, and the rising
edge of the clock, which loads the registers from the C bus. The other subcycle
boundaries are implicitly determined by the inherent propagation times of the cir-
cuits involved. It is the design engineers' responsibility to make sure that the time
Δ

Δ w +Δ x +Δ

z comes sufficiently in advance of the rising edge of the clock
to have the register loads work reliably all the time.

w +Δ x +Δ y +Δ

Memory Operation

Our machine has two different ways to communicate with memory: a 32-bit,
word-addressable memory port and an 8-bit, byte-addressable memory port. The
32-bit port is controlled by two registers, MAR ( Memory Address Register ) and
MDR ( Memory Data Register ), as shown in Fig. 4-1. The 8-bit port is controlled
by one register, PC , which reads 1 byte into the low-order 8 bits of MBR . This port
can only read data from memory; it cannot write data to memory.
Each of these registers (and every other register in Fig. 4-1) is driven by one or
two control signals . An open arrow under a register indicates a control signal that
enables the register's output onto the B bus. Since MAR does not have a connection
to the B bus, it does not have an enable signal. H does not have one either because,
being the only possible left ALU input, it is always enabled.
A solid black arrow under a register indicates a control signal that writes (i.e.,
loads) the register from the C bus. Since MBR cannot be loaded from the C bus, it
does not have a write signal (although it does have two other enable signals, de-
scribed below). To initiate a memory read or write, the appropriate memory regis-
ters must be loaded, then a read or write signal issued to the memory (not shown in
Fig. 4-1).
MAR contains word addresses, so that the values 0, 1, 2, etc. refer to consecu-
tive words. PC contains byte addresses, so that the values 0, 1, 2, etc. refer to con-
secutive bytes. Thus puttinga2in PC and starting a memory read will read out
byte 2 from memory and put it in the low-order 8 bits of MBR . Puttinga2in MAR
and starting a memory read will read out bytes 8-11 (i.e., word 2) from memory
and put them in MDR .
This difference in functionality is needed because MAR and PC will be used to
reference two different parts of memory. The need for this distinction will become
clearer later. For the moment, suffice it to say that the MAR / MDR combination is
used to read and write ISA-level data words and the PC / MBR combination is used