Hardware Reference
In-Depth Information
Bus request
Bus grant
Arbiter
Bus grant
may or may not
be propagated along
the chain
1
2
3
4
5
I/O devices
(a)
Bus request level 1
Bus request level 2
Bus grant level 2
Arbiter
Bus grant level 1
1
2
3
4
5
(b)
Figure 3-40.
(a) A centralized one-level bus arbiter using daisy chaining.
(b) The same arbiter, but with two levels.
As an aside, it is not technically necessary to wire the level 2 bus grant line
serially through devices 1 and 2, since they cannot make requests on it. However,
as an implementation convenience, it is easier to wire all the grant lines through all
the devices, rather than making special wiring that depends on which device has
which priority.
Some arbiters have a third line that a device asserts when it has accepted a
grant and seized the bus. As soon as it has asserted this acknowledgement line, the
request and grant lines can be negated. As a result, other devices can request the
bus while the first device is using the bus. By the time the current transfer is fin-
ished, the next bus master will have already been selected. It can start as soon as
the acknowledgement line has been negated, at which time the following round of
arbitration can begin. This scheme requires an extra bus line and more logic in
each device, but it makes better use of bus cycles.
In systems in which memory is on the main bus, the CPU must compete with
all the I/O devices for the bus on nearly every cycle. One common solution for this
situation is to give the CPU the lowest priority, so it gets the bus only when nobody
else wants it. The idea here is that the CPU can always wait, but I/O devices fre-
quently must acquire the bus quickly or lose incoming data. Disks rotating at high
speed cannot wait. This problem is avoided in many modern computer systems by
