Hardware Reference
In-Depth Information
O
0
I
0
O
1
I
1
O
2
I
2
O
3
O
3
CK
Q
D
Q
D
Q
D
Q
D
CK
CLR
CK
CLR
CK
CLR
CK
CLR
CLR
CLR
CLR
CLR
CK
CK
CK
CK
QD
QD
QD
QD
CLR O
4
I
4
O
5
I
5
O
6
I
6
O
7
I
7
Figure 3-27.
An 8-bit register constructed from single-bit flip-flops.
memory organization that meets this criterion is shown in Fig. 3-28. This example
illustrates a memory with four 3-bit words. Each operation reads or writes a full
3-bit word. While the total memory capacity of 12 bits is hardly more than our
octal flip-flop, it requires fewer pins and, most important, the design extends easily
to large memories. Note the number of words is always a power of 2.
While the memory of Fig. 3-28 may look complicated at first, it is really quite
simple due to its regular structure. It has eight input lines and three output lines.
Three inputs are data:
I
0
,
I
1
, and
I
2
; two are for the address:
A
0
and
A
1
; and three
are for control:
CS
for Chip Select,
RD
for distinguishing between read and write,
and
OE
for Output Enable. The three outputs are for data:
O
0
,
O
1
, and
O
2
. Itisin-
teresting to note that this 12-bit memory requires fewer signals than the previous
8-bit register. The 8-bit register requires 20 signals, including power and ground,
while the 12-bit memory requires only 13 signals. The memory block requires
fewer signals because, unlike the register, memory bits share an output signal. In
this memory, 4 memory bits each share one output signal. The value of the address
lines determine which of the 4 memory bits is allowed to input or output a value.
To select this memory block, external logic must set
CS
high and also set
RD
high (logical 1) for read and low (logical 0) for write. The two address lines must
be set to indicate which of the four 3-bit words is to be read or written. For a read
operation, the data input lines are not used, but the word selected is placed on the
data output lines. For a write operation, the bits present on the data input lines are
loaded into the selected memory word; the data output lines are not used.
Now let us look at Fig. 3-28 closely to see how it works. The four word-select
AND
gates at the left of the memory form a decoder. The input inverters have been
placed so that each gate is enabled (output is high) by a different address. Each
gate drives a word select line, from top to bottom, for words 0, 1, 2, and 3. When
the chip has been selected for a write, the vertical line labeled
CS
⋅
RD
will be high,
