Digital Signal Processing Reference
In-Depth Information
Disconnect the pushbutton from the lpm_counter0's clock pin and connect it to
the pushbutton input pin, PB, on the debounce symbol. Now connect the
PB_DEBOUNCED pin to the lpm_counter0's clock pin. The debounce circuit
needs a 100Hz clock signal for the time averaging filter. The clock needed is
much slower than a 25-50MHz system clock, so a clock prescalar is needed. A
clock prescalar is a logic circuit that divides a clock signal.
Add the
clk_div
symbol from the project library to the schematic. Connect the
100Hz input pin on the debounce symbol to the 100Hz output pin on the clock
prescalar. Connect the 48MHz clock input on the
clk_div
symbol to the
clk_48MHz (or clk_50Mhz on DE1 and DE2) input pin.
The internal VHDL design in the debounce module generates the switch
debounce circuit. The debounce circuit contains a 4-bit shift register that is
clocked at 100Hz. The shift register shifts in the inverted pushbutton output.
When any of the four bits of the shift register (i.e., four 10 ms time-spaced
samples of the pushbutton's output) are High the output of the debounce circuit
changes to High. When all four bits of the shift register are Low the output
goes Low. This delays the High to Low change until after the switch contact
bounce stops.
If the external input signal being counted or used for a reset was a fast clock
that was not synchronized to the internal FPGA clock, another problem with the
simple counter circuit could appear that would cause problems. If the external
input signal changes right at a clock edge, it could violate the flip-flop setup
and hold times and cause upredictable results (metastability). The traditional
solution for this problem is to feed any external input signals through two
cascaded D flip-flops that are clocked by the system clock. This reduces the
probability of a such an error to only once in several years even for a rapidly
changing clock input signal. This circuit is sometimes called a synchronizer. A
very slowly changing signal, such as a user input switch, has a very low
probability of such an event occuring even without a synchronizer circuit, but it
could still occur and would require a synchronizer in mission critical
applications where such a failure could be catastrophic.
4.8 Testing the Modified Design on the FPGA Board
Verify that your schematic has the same connections to the new debounce and
clock divide symbols as seen in Figure 4.8. Compile the design and download
the design to the board again. Hit the count switch several times to clock the
counter and watch the LCD display as it counts up. It should now count up
reliably by one whenever the pushbutton is hit. Hit the reset switch and verify
that the count resets to zero.
The FPGAcore functions LCD_Display or DEC_7SEG, clk_div, and debounce
will be useful in future design projects using the FPGA board. They can be used
in any VHDL, Verilog, or schematic designs by using the graphical editor and
FPGAcore symbols or by using an HDL component instantiation statement.
