Digital Signal Processing Reference
In-Depth Information
Since the FPGA's clock input on the DE2 and UP3 is only 50 or 48 MHz for
the LCD_Display core, this simple counter cannot be overclocked. Close and
exit the timing analyzer.
4.6 Testing the Initial Design on the Board
Download the design to the FPGA board. If you need help downloading to the
board, refer back to Sections 1.5 to 1.8 depending on board type.
The name of the specific switch assigned for each FPGA board is shown in
Table 4.2. Hit or turn on the count switch several times to clock the counter and
watch the count display as it counts up. When the switch is hit, it will
occasionally count up by more than one. This is a product of mechanical
bounce in the switch. A switch contains a metal spring that actually forces
contact and bounces several times before stabilizing. The high-speed logic
circuits will react to the switch contact bounce just as if several clock signals
have occured. This makes the counter count up by more than one randomlly.
Table 4.2 Location of Switches on each FPGA board.
I/O Device
DE1
DE2
UP3
UP2 & 1
SW4 - count up
SW0
SW0
SW4
Flex PB1
SW8 - reset
KEY3
KEY3
SW8
Flex PB2
Figure 4.7
Oscillosope display of switch contact bounce.
