Digital Signal Processing Reference
In-Depth Information
given the name of one or more of the bus elements. As an example, the counter
output MSB signal line is labeled q[7]. To label a bus or node, right click on the
node or bus line and select
Properties
. You can then type in or edit the name.
When signal lines have the same name, they are automatically connected in the
graphic editor. A physical node line connecting a node and a bus with the same
name is optional. Leaving it out often times makes a complex schematic easier
to follow since there will be fewer lines crossing on the schematic. Node and
bus names must be assigned first when connecting a node to a bus.
4.5 Testing the Pushbutton Counter and Displays
Compile the design with
Processing
Start Compilation.
Wait a few seconds
for the “Full Compilation was successful” message to appear. Select
Processing
Classic Timing Analyzer Tool
. This counter circuit is a
sequential design. The primary timing issue in sequential circuits is the
maximum clock rate. Whenever you compile, a timing analysis tool
automatically runs that will determine the maximum clock frequency of the
logic circuit.
Figure 4.6
Timing analysis of a Sequential Circuit
The Timing Analyzer shows the maximum clock frequency of this logic circuit
to be approximately 120 MHz. Clock rates you will obtain will vary depending
on the FPGA device type, the complexity and size of the logic circuits, the
speed grade of the chip, and the CAD tool version and settings. In this design,
the clock is supplied by a manual switch input so a clock input of only a few
hertz will be used for the counter.
