Digital Signal Processing Reference
In-Depth Information
The typical FPGA CAD tool design flow is shown in Figure 3.13. After design
entry using an HDL or schematic, the design is automatically translated,
optimized, synthesized, and saved as a netlist. (A netlist is a text-based
representation of a logic diagram.) A functional simulation step is often added
prior to the synthesis step to speed up simulations of large designs.
An automatic tool then fits the design onto the device by converting the design
to use the FPGA's logic elements, first by placing the design in specific logic
element locations in the FPGA and then by selecting the interconnection
network routing paths. The place and route process can be quite involved and
can take several minutes to compute on large designs. On large devices,
combinatorial explosion (exponential growth) will prevent the tool from
examining all possible place and route combinations. When designs require
critical timing, some tools support timing constraints that can be placed on
critical signal lines. These optional constraints are added to aid the place and
route tool in finding a design placement with improved performance.
Design
Entry
Optimization &
Synthesis
Device
Fitting
Device
Programming
Translation
Simulation
Figure 3.13
CAD tool design flow for FPGAs.
After place and route, simulation can be performed using actual gate and
interconnect time delays from a detailed timing model of the device. Although
errors can occur at any step, the most common path is to find errors during an
exhaustive simulation. The final step is device programming and hardware
verification on the FPGA.
3.6 Next Generation FPGA CAD tools
A few HDL synthesis tools now support behavioral synthesis. Unlike the more
widely used register transfer level (RTL) models contained in this topic,
behavioral synthesis models do not specify the exact states and sequence of
register transfers. A separate constraint file specifies the number of clocks
needed to obtain selected signals and the tool automatically generates the state
machines, logic, and register transfers needed.
Although not currently in widespread use for current designs, newer FPGA
CAD tools are also appearing based on other languages such as C and Java.
Some of these system-level tools output VHDL or Verilog models as an
intermediate step. New HDLs such as SystemVerilog (
www.systemverilog.org
)
and SystemC (
www.systemC.org
) provide enhanced support for verification.
Tools that automatically generate an FPGA design from other engineering tools
such as MATLAB-Simulink or LabVIEW have also been introduced. These
graphical based tools are primarily aimed at DSP application development for
FPGAs using a library of specialized DSP blocks.
