Digital Signal Processing Reference
In-Depth Information
Row Interconnect
Direct Link
Interconnect
from
Adjacent
Block
Direct Link
Interconnect
from
Adjacent
Block
Direct Link
Interconnect
to Adjacent
Block
Direct Link
Interconnect
to Adjacent
Block
Local
Interconnect
LAB
Local
Interconnect
LAB
Figure 3.9
Cyclone Logic Array Blocks (LAB) and Interconnects.
3.4 Xilinx 4000 Architecture - A Look-Up Table FPGA Device
The Xilinx 4000 Family was a popular first generation FPGA device family
with 2,000 to 180,000 usable gates. It is configured by programming internal
SRAM. Figure 3.10 is a photograph of a six-inch silicon wafer containing
several XC4010E 10,000 gate FPGA chip dice. Figure 3.11 is a contrast-
enhanced view of a single XC4010E die. If you look closely, you can see the 20
by 20 array of logic elements and the surrounding interconnect lines. Die that
pass wafer-level inspection and testing are sliced from the wafer and packaged
in a chip. FPGA yields are typically 90% or higher after the first few
production runs.
As seen in Figure 3.12, this device contains a more complex logic element
called a configurable logic block (CLB). Each CLB contains three SRAM-
based lookup tables. Outputs from the LUTs can be fed into two flip-flops and
routed to other CLBs. A CLB's lookup tables can also be configured to act as a
16 by 2 RAM or a dual-port 16 by 1 RAM. High-speed carry logic is provided
between adjacent CLBs.
