Digital Signal Processing Reference
In-Depth Information
RAM Contents
Add
r
es
s
A
B
C
D
4 Input
LUT
(16 x 1 RAM)
Data
F
AB
CD
F
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
A
B
0
1
1
0
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
F
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
C
D
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
Figure 3.8
Using a look-up table (LUT) to model a gate network.
More complex gate networks require interconnections with additional
neighboring logic elements. The output of the LUT can be fed into a D flip-flop
and then to the interconnection network. The clock, Clear, and Preset can be
driven by internal logic or an external I/O pin. The flip-flop can be
programmed to act as a D flip-flop, T flip-flop, JK flip-flop, or SR latch. Carry
and Cascade chains connect to all LEs in the same row.
Figure 3.9 shows a Logic Array Block (LAB). A logic array block is composed
of ten logic elements (LEs). Both programmable local LAB and chip-wide row
and column interconnects are available. Carry chains are also provided to
support faster addition operations.
Input-output elements (IOEs) are located at each of the device's I/O pins. IOEs
contain a programmable tri-state driver and an optional 1-bit flip-flop register.
Each I/O pin can be programmed as input, output, output with a tri-state driver,
or even tri-state bi-directional with or without a register. Four clock I/O pins
connect to the eight low-skew global clock buffer lines that are provided in the
device.
