Digital Signal Processing Reference
In-Depth Information
1.14 The Floorplan Editor
A floorplan editor is a visual tool to assist expert users in manually placing and
moving portions of logic circuits to different logic cells inside the FPGA. This
is done in an attempt to achieve faster timing or better utilization of the FPGA.
Floorplanning is typically used only on very large designs that contain
subsections of hardware with critical high-speed timing. Since the interconnect
delays are as large as the design's logic delays, logic element and I/O pin
placement is very critical in high speed designs. Vertical and horizontal
interconnect buses are used through the FPGA to connect Logic Elements.
For all but expert users, the compiler's automatic place-and-route tools should
be used. Automatic place-and-route was already performed by the fitter in the
compile process of the tutorial. Timing constraints for critical signals can also
be specified in some FPGA place and routing tools to help the fitter meet the
design's timing goals.
To see the fitter's automatic placement of the design inside the FPGA, select
Assignment
Back-Annotate Assignments
click
OK
and then
Assignments
Timing Closure Floorplan.
In the display that opens, zoom in
and scroll around to find the colored logic element and gray shaded I/O pins
used in your design. Find and select the colored Logic Element (LE), then
View
Routing
show fan in
and then
show fan out,
and a view like Figure
1.28 showing the design can be produced for the DE1.
There is a lot of empty space since the Cyclone II EP2C20 FPGA contains
18,752 Logic Elements (LEs) and 315 I/O pins. Only 1 LE and three I/O pins
were used in this design. If you move the logic cell or I/O pins to other
locations, it will make small changes to the circuit timing because of changes
in the interconnect delays inside the FPGA.
Due to the vast number of possible combinations, FPGA CAD tools cannot
explore every possible placement and routing option. The Quartus II Design
Space Explorer tool can also be used to search and explore other design
options in the design space. Large FPGA designs containing millions of gates
can require several hours or even days of CPU time to examine many of the
different place and route alternatives in the design space.
