Digital Signal Processing Reference
In-Depth Information
1.13 Timing Analysis
With every physical device, there are timing considerations. An FPGA's timing
is affected by:
•
Input buffer delays,
•
Signal routing interconnect delays within the FPGA,
•
The internal logic delays (in this case the OR), and
•
Output buffer delays.
The timing analysis tool can be used to determine:
•
The physical delay times and
•
The maximum clock rates in your design.
Starting the Analyzer
At the top menu, select
Processing
Compilation Report
and then
in the
Compilation Report window
, expand Timing Analyzer
and
select tpd
. A
matrix of input to output delay times for the project will be computed and
displayed as seen in Figure 1.27.
Figure 1.27
Timing analyzer showing input to output signal propagation timing delays.
Note that this is the same delay time seen in the simulator. These times include
the input-to-output buffer delays at the pins and the interconnect delays inside
the FPGA. The internal OR logic delay is only around a nanosecond relative to
the rest of the device delay.
The exact time shown will vary with different versions of the Altera CAD
tools, the different FPGA chips found on the various boards, and different
FPGA chip speed grades. Other timing analysis options include setup times,
hold times, and clock rates for sequential circuits.
