Digital Signal Processing Reference
In-Depth Information
import an existing software project into a new design project's software
directory
using
File
Import
. You will need to clean and rebuild the software
project since the system library changes for each new hardware design.
IMPORTANT:
In the reference hardware design, SW9 is used as the Nios II
processor's reset signal. Before code can be downloaded to the processor, it
must be brought out of reset by setting SW9 in the up (or on) position.
A
LL
S
OURCE FILES FOR
T
HIS
N
IOS
II
H
ARDWARE
R
EFERENCE
D
ESIGN
CAN BE FOUND ON THE
DVD
IN THE
\DE
X
\C
HAP
17
D
IRECTORY
.
17.20 For additional information
This chapter has provided a brief overview of Nios II hardware development.
Additional information can be found at Altera's website (
www.altera.com
) in
the
Nios II Processor Reference Handbook, Embedded Peripherals Handbook
and
Hardware Development Tutorial
. Nios II components for the DE boards
and other reference designs can be found at Altera's University Program
website. The Nios Community Forum (
www.niosforum.com
) also contains
useful information and downloads for Nios II projects.
17.21 Laboratory Exercises
1.
Add two 8-bit PIOs to the Nios II hardware design that connect to the 5 volt I/O pins on
the board's header connector. Setup one port for input and one port for output. Connect
the PIO port's I/O pins to eight input pins and eight output pins on the header. This is a
handy way to interface external devices and sensors like those used in the FPGA robot
projects in Chapter 13 to the FPGA board's Nios II processor.
2.
Add a PIO port to the Nios II hardware design and use the PIO port's I/O bits to design
an I
2
C hardware interface to the FPGA board's real-time clock chip. Software will be
needed to send I
2
C commands, the PIO port just provides a hardware interface to the I
2
C
SDA and SLC bits (see Section 12.4).
3.
Add a parallel port to the Nios II hardware design. Use two 8-bit ports, one for data and
one for status and control bits. Connect the PIO port's I/O bits to the parallel port
connector on the FPGA board. Software will be needed to monitor and control the
handshake lines (see Section 12.1) when connecting to a device like a parallel printer.
4.
Add an SPI interface to the Nios II hardware design and use it to interface to an external
SPI device connected to one of the FPGA board's expansion connectors.
