Digital Signal Processing Reference
In-Depth Information
tools to ease the customization and use of their cores, including high-level
compilers targeted at the custom cores.
In the case of Altera and Xilinx, the Processor Core Configuration Tool block
shown in Fig. 15.1 is realized in a user-friendly GUI interface that allows the
designer to customize the processor for a particular project. The configurable
parameters can include the datapath width, memory, address space, and
peripherals (including arbitrarily defined general-purpose I/O, UARTs, Ethernet
controllers, memory controllers, etc.). Once the processor parameters are
specified in the GUI interface, the processor core is generated in the form of an
HDL file (in Altera) or a netlist file (in Xilinx). This file can then be included
within a traditional HDL or schematic design using the standard CAD tools.
Specific pin assignments and additional user logic can be included at this point
like any other FPGA design. Next, the full hardware design (processor core and
any additional user logic) is compiled (synthesis, place and route, etc.), and the
FPGA can be programmed with the resulting file using the standard tools. The
hardware design is complete, and the FPGA logic has been determined.
High-level Compiler for Processor Core
As shown on the right side of Fig. 15.1, the next step is to write and compile
the software that will be executed on the soft processor core. When the
Processor Core Configuration Tool generates the HDL or netlist files, it also
creates a number of library files and their associated C header files that are
customized for the specific processor core generated. A C/C++ compiler
targeted at this processor is also provided. The designer can then program stand
alone programs to run on the processor. Optionally, the designer can compile
code for an operating system targeted for the processor core. Several operating
systems for the Nios II are available from third-party vendors along with the
community supported open source eCos (
www.niosforum.com
).
15.3 Initializing Memory
Once a program/data binary file has been generated, it must be loaded into the
processor's program and data memories. This loading can be done several ways
depending on the memory configuration of the processor at hand.
On-chip Memory
If the application program is small and can fit into the memory blocks available
on the FPGA, then the program can be initialized in the memory when the
hardware configuration is programmed. This initialization is done through the
standard FPGA tools, such as Altera's Quartus II software or Xilinx's ISE
software. However, on-chip memory is typically very limited, and this solution
is not usually an option.
Bootloader
In a prototyping environment, the application program will most likely be
modified a number of times before the final program is complete. In this case,
the ability to download the application code from a PC to the memory on an
