Digital Signal Processing Reference
In-Depth Information
functionality is still needed, and in the case of both Altera and Xilinx, the same
CAD tools (Quartus II or ISE) are used to implement these blocks.
Processor Core Configuration Tools
Today, a number of pre-defined processor cores are available from various
sources. GPL-licensed public processor cores can be found on the web (i.e.,
www.opencores.org
and
www.leox.org
), while companies such as Altera (Nios
II processor), Xilinx (MicroBlaze processor), and Tensilica (Xtensa processor)
provide their processors and/or development tools for a fee.
Additional User
Hardware
(optional)
Hardware
Design
Software
Design
Design
Entry
Too l
Processor Core
Configuration
Too l
Application
Program Source
Code
HDL or Schematic
H
D
L
or Netlist
FPGA
Synthesis
Too l
Operating
System Kernel
and Libraries
(optional)
Processor
Config
.
Data
C/C++ Compiler
for Processor
Traditional
FPGA Tool
Flow
Netlist
FPGA
Place and Route
Too l
Binary
Program/Data
Files
Program
FPGA
and
Initialize
Memory
Processor
Memory
Figure 15.1
The CAD tool flow for SOPC design is comprised of the traditional design process for
FPGA-based systems with the addition of the Processor Core Configuration Tool and software design
tools. In this figure, the program and data memory is assumed to be on-chip for simplicity.
Processor cores provided by FPGA manufacturers are typically manually
optimized for the specific FPGA family being used, and as such, are more
efficiently implemented on the FPGA than a student-designed core (especially
given the time and resource constraints of most class projects). The simple
computer and MIPS processor cores developed earlier in this topic were
designed to be easy for students to understand and were not optimized for any
particular FPGA. Additionally, FPGA companies provide extensive support
