A RISC Design: Synthesis of the MIPS Processor Core - Rapid Prototyping of Digital Systems - page 290

SIGNAL Regwrite : STD_LOGIC ;

SIGNAL Zero : STD_LOGIC ;

SIGNAL MemWrite : STD_LOGIC ;

SIGNAL MemtoReg : STD_LOGIC ;

SIGNAL MemRead : STD_LOGIC ;

SIGNAL ALUop : STD_LOGIC_VECTOR ( 1 DOWNTO 0 );

SIGNAL Instruction : STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

BEGIN
-- copy important signals to output pins for easy
-- display in Simulator
Instruction_out <= Instruction;
ALU_result_out <= ALU_result;
read_data_1_out <= read_data_1;
read_data_2_out <= read_data_2;
write_data_out <= read_data WHEN MemtoReg = '1' ELSE ALU_result;

Branch_out <= Branch;

Zero_out <= Zero;

RegWrite_out <= RegWrite;

MemWrite_out <= MemWrite;

-- connect the 5 MIPS components

IFE : Ifetch

PORT MAP ( Instruction => Instruction,

PC_plus_4_out => PC_plus_4,

Add_result => Add_result,

Branch => Branch,

Zero => Zero,

PC_out => PC,

clock => clock,

reset => reset );

ID : Idecode

PORT MAP ( read_data_1 => read_data_1,

read_data_2 => read_data_2,

Instruction => Instruction,

read_data => read_data,

r l t => ALU_result,

RegWrite => RegWrite,

MemtoReg => MemtoReg,

RegDst => RegDst,

Sign_extend => Sign_extend,

clock => clock,

reset => reset );

CTL: control

PORT MAP ( Opcode => Instruction( 31 DOWNTO 26 ),

RegDst => RegDst,

ALUSrc => ALUSrc,

MemtoReg => MemtoReg,

RegWrite => RegWrite,

MemRead => MemRead,