A RISC Design: Synthesis of the MIPS Processor Core - Rapid Prototyping of Digital Systems - page 289

RegDst : IN STD_LOGIC ;

Sign_extend : OUT STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

clock, reset : IN STD_LOGIC );

END COMPONENT ;

COMPONENT control

PORT ( Opcode : IN STD_LOGIC_VECTOR ( 5 DOWNTO 0 );

RegDst : OUT STD_LOGIC ;

ALUSrc : OUT STD_LOGIC ;

MemtoReg : OUT STD_LOGIC ;

RegWrite : OUT STD_LOGIC ;

MemRead : OUT STD_LOGIC ;

MemWrite : OUT STD_LOGIC ;

Branch : OUT STD_LOGIC ;

ALUop : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );

clock, reset : IN STD_LOGIC );

END COMPONENT ;

COMPONENT Execute

PORT ( Read_data_1 : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

Read_data_2 : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

Sign_Extend : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

Function_opcode : IN STD_LOGIC_VECTOR ( 5 DOWNTO 0 );

ALUOp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );

ALUSrc : IN STD_LOGIC ;

Zero : OUT STD_LOGIC ;

ALU_Result : OUT STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

Add_Result : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

PC_plus_4 : IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

clock, reset : IN STD_LOGIC );

END COMPONENT ;

COMPONENT dmemory

PORT ( read_data : OUT STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

address : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

write_data : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

MemRead, Memwrite : IN STD_LOGIC ;

Clock,reset : IN STD_LOGIC );

END COMPONENT ;

-- declare signals used to connect VHDL components

SIGNAL PC_plus_4 : STD_LOGIC_VECTOR ( 9 DOWNTO 0 );

SIGNAL read_data_1 : STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

SIGNAL read_data_2 : STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

SIGNAL Sign_Extend : STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

SIGNAL Add_result : STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

SIGNAL ALU_result : STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

SIGNAL read_data : STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

SIGNAL ALUSrc : STD_LOGIC ;

SIGNAL Branch : STD_LOGIC ;

SIGNAL RegDst : STD_LOGIC ;