Legacy Digital I/O Interfacing Standards - Rapid Prototyping of Digital Systems - page 238

7-bit address is sent and the eighth bit is a R/W bit (0=read, 1=write). Some IC
datasheets just append this final R/W bit to the address field and show an 8-bit
address field (with even 8-bit addresses for read and odd for write).
The last bit in all data and address transfers, bit nine, is an ACK from the slave.
The slave normally drives ACK Low on the last SCL cycle to indicate it is
ready for another byte. If ACK is not Low, the master should send a stop
sequence to terminate the transfer.
As seen in Figure 12.4, when a master wants to write data to a slave device, it
issues the following bus transactions:
1. Master sends a start sequence.
2. Master sends the 7-bit I 2 C address (high bits first) of the slave with the
R/W bit set Low.
3. Master sends the 8-bit internal register number to write.
4. Master sends 8-bit data value(s). Highest bits first.
5. Master sends a stop sequence.
When a master wants to read data from a slave device, it issues the following
bus transactions:
1. Master sends a start sequence.
2. Master sends the 7-bit I 2 C address of the slave (high bits first) with the
R/W bit set Low.
3. Master sends the 8-bit internal register number to read.
4. Master sends a start sequence.
5. Master sends the 7-bit I 2 C address of the slave (high bits first) with the
R/W bit set High.
6. Master reads the 8-bit data value(s). Highest bits first.
7. Master sends a stop sequence.
In the full I 2 C standard, multiple bus masters are also supported with collision
detection and bus arbitration. Collision occurs when two masters attempt to
drive the bus at the same time. Arbitration schemes must decide which device
can drive the bus when multiple masters are present. Some of the newest I 2 C
devices can support a high-speed 3.4 MHz clock rate, 10-bit addresses,
programmable slave addresses, and lower supply voltages. The System
Management Bus (SMB) bus developed by Intel in 1995 that is used for
temperature, fan speed, and voltage measurements on many PC motherboards is
based on the I 2 C bus. On the UP3 board, the real-time clock chip and the serial
EEPROM chip use an I 2 C bus interface. Many new TVs, automobiles, and other
consumer electronics also contain I 2 C interfaces between chips for control
features.