Digital Signal Processing Reference
In-Depth Information
12.4 I
2
C Bus Interface
The Inter IC (I
2
C) bus is a widely used standard developed by Phillips in the
1980s for connecting ICs on the same circuit board. Many small ICs now
include I
2
C pins to transfer data serially to other ICs. For lower bandwidth
signals, a serial interface has an advantage in that it requires fewer interconnect
lines. The I
2
C bus uses two signal wires called SCL and SDA. SCL is the clock
line and SDA is the 1-bit serial data & address line. A common ground signal is
also needed. The SCL and SDA lines are open drain. This means that the output
is only driven Low, never High. An external pull-up resistor pulls the lines
High whenever there is not a device driving the lines Low.
In an FPGA with tri-state output pins, you can simulate open drain outputs by
tri-stating the output whenever the bit should go High and only driving the
output signal Low. Even though there are multiple devices on the I
2
C bus, only
one pull-up resistor is used for the entire I
2
C bus.
Devices on the I
2
C bus are masters or slaves. The slaves are the devices that
respond to bus requests from the master. Each slave is assigned its own unique
7-bit I
2
C bus address. Since both address and data information is transferred
over the bus, the protocol is a bit more involved than SPI. When the master
needs to talk to a slave, it issues a start sequence on the I
2
C bus. In a start
sequence, SDA goes from High to Low while SCL is High. To stop an I
2
C
sequence, the master sends a stop sequence command. In a stop sequence, SDA
goes from Low to High while SCL is High. Start and stop sequences are the
only times a change may occur in SDA while SCL is High.
The master drives the SCL clock line to transfer each new I
2
C serial bit. To
force a wait, a slave device can drive SCL Low. Therefore, before each new I
2
C
SCL clock, the master checks to see if SCL is being forced Low by a slave. If it
is, the master must wait. SCL clocks are typically up to 100 kHz with 400 kHz
available on some new devices.
SD A
MSB
ACK Signal
from Receiver
Byte Complete
ACK Signal from
Receiver
Clock Line held
Low while serviced
SCL
1
2
7
8
9
1
2
37
8
9
S
P
ACK
R/W ACK
START
STOP
Address
Data
Figure 12.4
I
2
C interface serial transmission of an 8-bit data value
All address and data transfers contain eight bits with a final acknowledge
(ACK) handshake bit for a total of nine bits. All address and data transfers
send the High bits first, one per SCL clock bit High. In an address transfer, the
