Digital Signal Processing Reference
In-Depth Information
For a video mouse cursor such as is seen in the PC, the motion value will need
to be added to the current value every time a new data packet is received.
Assuming 640 by 480 pixel resolution, two 10-bit registers containing the
current cursor row and column addresses are needed. These registers are
updated every packet by adding the sign extended 8-bit X and Y motion values
found in bytes 2 and 3 of the data packet. The cursor normally would be
initialized to the center of the video screen at power-up.
11.12 An Example Design Using the Mouse FPGAcore
In this example design, the mouse drives the LCD display on the DE2 or UP3
boards. The mouse cursor powers up to the center position of the 640 by 480
video screen. Note that the PS/2 mouse clock and data pins must be bi-
directional. The block Mouse_LCD_interface rearranges the mouse core output
signals for use by the LCD_Display core function. On FPGA boards without an
LCD module, the seven segment LED displays are used instead.
MOU SE
BIDIR
PS2_DATA
clock_48Mhz
reset
mouse_data
mouse_clk
VCC
BIDIR
PS2_CLK
VCC
lef t_button
right_button
mouse_cursor_row[9..0]
mouse_cursor_column[9..0]
lef t_button
right_button
inst1
CLK_48Mhz
INPUT
VCC
LCD_Display
SW8
INPUT
OUTPUT
LCD_RS
reset
clk_48Mhz
Hex_Display _Data[num_hex_digits*41..0]
LCD_RS
LCD_E
LCD_RW
DATA_BUS[7..0]
VCC
OUTPUT
LCD_E
OUTPUT
VCC
LCD_RW
BIDIR
DATA_BUS[7..0]
inst
mouse_LCD_interf ace
mouse_cursor_row[9..0]
mouse_cursor_column[9..0]
lef t_button
right_button
Hex_Display _Data[23..0]
lef t_button
right_button
inst3
Figure 11.7
Example design using the Mouse FPGAcore.
