Digital Signal Processing Reference
In-Depth Information
and 00 are sent out prior to downloading and need not be considered in the
interface. This assumes that the mouse is plugged in before applying power to
the UP3 board and downloading the design.
The default power-up mode is streaming mode disabled. To get the mouse to
start sending 3-byte data packets, the streaming mode must be turned on by
sending the enable streaming mode command, F4, to the mouse from the FPGA
chip. The clock tri-state line is driven Low by the FPGA for at least 60us to
inhibit any data transmissions from the mouse. This is the only case when the
FPGA chip should ever drive the clock line. The data line is then driven Low
by the FPGA chip to signal that the system has a command to send the mouse.
Clock
Data
Inhibit
I/O
0 0 1 0 1 1 1 1
System Data
Rea dy
to Send=0
Odd Par ity
Bit=0
Stop
Bit=1
8 Data Bi ts in Low to High Or der
Command Code shown is F4H
Figure 11.6
Transmission of Mouse Initialization Command.
The clock line is driven High for four clocks at 24 MHz and then tri-stated to
simulate an open collector output. This reduces the rise time and reflections on
the mouse cable that might be seen by the fast FPGA chip logic as the clock
line returns to the High state. As an alternative, the mouse clock input to the
FPGA could be briefly disabled while the clock line returns to the High state.
Next the mouse, seeing data Low and clock High, starts clocking in the serial
data from the FPGA chip. The data is followed by an odd parity bit and a High
stop bit. The handshake signal of the data line starting out Low takes the place
of the start bit when sending commands to the mouse.
With the FPGA chip clock and data drivers both tri-stated, the mouse then
responds to this message by sending an acknowledge message code, FA, back
to the FPGA chip. Data from the mouse includes a Low start bit, eight data bits,
an odd parity bit, and a High stop bit. The mouse, as always, drives the clock
line for the serial data transmission. The mouse is now initialized.
11.11 Mouse Data Packet Processing
As long as the FPGA chip clock and data drivers remain tri-stated, the mouse
then starts sending 3-byte data packets at the power-up default sampling rate of
100 per second. Bytes 2 and 3 of the data packet contain X and Y motion values
as was seen in Table 11.6. These values can be positive or negative, and they
are in two's complement format.
