Interfacing to the PS/2 Keyboard and Mouse - Rapid Prototyping of Digital Systems - page 221

key board

key board_clk key board_clk

key board_dat a

scan_code[ 7. . 0] scan_code[ 7. . 0]

scan_ready key board_dat a

clock_48Mhz

scan_ready

clock_48Mhz
reset reset

read read

inst

Figure 11.4 Keyboard FPGAcore

LIBRARY IEEE ;
USE IEEE . STD_LOGIC_1164 . ALL ;
USE IEEE .STD_LOGIC_ARITH. ALL ;
USE IEEE .STD_LOGIC_UNSIGNED. ALL ;

ENTITY keyboard IS

PORT ( keyboard_clk, keyboard_data, clock_48MHz ,

reset, read : IN STD_LOGIC ;

scan_code : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

scan_ready : OUT STD_LOGIC );

END keyboard;

ARCHITECTURE a OF keyboard IS

SIGNAL INCNT : STD_LOGIC_VECTOR ( 3 DOWNTO 0 );

SIGNAL SHIFTIN : STD_LOGIC_VECTOR ( 8 DOWNTO 0 );

SIGNAL READ_CHAR, clock_enable : STD_LOGIC ;

SIGNAL INFLAG, ready_set : STD_LOGIC ;

SIGNAL keyboard_clk_filtered : STD_LOGIC ;

SIGNAL filter : STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

BEGIN

PROCESS ( read, ready_set )

BEGIN

IF read = '1' THEN

scan_ready <= '0';

ELSIF ready_set 'EVENT AND ready_set = '1' THEN

scan_ready <= '1';

END IF ;

END PROCESS ;

--This process filters the raw clock signal coming from the

-- keyboard using a shift register and two AND gates

Clock_filter:

PROCESS

EGI N

W I T UNTIL clock_48MHz 'EVENT AND clock_48MHz = '1';

clock_enable <= NOT clock_enable;

I F clock_enable = '1' THEN

filter ( 6 DOWNTO 0 ) <= filter( 7 DOWNTO 1 ) ;