A Simple Computer Design: The uP 3 - Rapid Prototyping of Digital Systems - page 182

END CASE ;

END IF ;

END PROCESS ;

-- memory address register is already inside synchronous memory unit
-- need to load its value based on current state
-- (no second register is used - not inside a process here)
WITH state SELECT

memory_address_register <= "00000000" WHEN reset_pc,

program_counter WHEN fetch,

instruction_register(7 DOWNTO 0) WHEN decode,

program_counter WHEN execute_add,

instruction_register(7 DOWNTO 0) WHEN execute_store,

program_counter WHEN execute_store2,

program_counter WHEN execute_load,

instruction_register(7 DOWNTO 0) WHEN execute_jump;

WITH state SELECT

memory_write <= '1' WHEN execute_store,

'0' WHEN Others;

END a;

Figure 9.11 VHDL Model of ΜP 3 Computer.

9.4 Verilog Model of the Μ P 3
To demonstrate the operation of the computer using Verilog, a Verilog model of
the ΜP 3 computer is shown in Figure 9.12. The computer's RAM memory is
implemented using the Altsyncram function which uses the FPGA's internal
memory blocks. The remainder of the computer model is basically a Verilog-
based state machine that implements the fetch, decode, and execute cycle. The
first few lines declare internal registers for the processor along with the states
needed for the fetch, decode and execute cycle. A long CASE statement is used
to implement the control unit state machine. A reset state is needed to initialize
the processor. In the reset state, several of the registers are reset to zero and a
memory read of the first instruction is started. This forces the processor to start
executing instructions at location 00 in a predictable state after a reset. A
second case statement at the end of the code makes assignments to the memory
address register based on the current state.

//uP3 Computer Design in Verilog
module scomp (clock,reset,program_counter,register_A,

memory_data_register_out, instruction_register);

input clock,reset;
output [7:0] program_counter;
output [15:0] register_A, memory_data_register_out, instruction_register;

reg [15:0] register_A, instruction_register;
reg [7:0] program_counter;
reg [3:0] state;