Digital Signal Processing Reference
In-Depth Information
data will appear on the memory data bus lines, and it will be latched into the
memory data register (MDR).
Fetch Next
Instruction
Decode
Instruction
Execute
Instruction
Figure 9.5
Processor Fetch, Decode and Execute Cycle.
Execution of the instruction may require an additional memory cycle so the
instruction is normally saved in the CPU's instruction register (IR). Using the
value in the IR, the instruction can now be decoded. Execution of the
instruction will require additional operations in the CPU and perhaps additional
memory operations.
The Accumulator (AC) is the primary register used to perform data calculations
and to hold temporary program data in the processor. After completing
execution of the instruction the processor begins the cycle again by fetching the
next instruction.
The detailed operation of a computer is often modeled by describing the
register transfers occurring in the computer system. A variety of register
transfer level (RTL) languages such as VHDL or Verilog are designed for this
application. Unlike more traditional programming languages, RTL languages
can model parallel operations and map easily into hardware designs. Logic
synthesis tools can also be used to implement a hardware design automatically
using an RTL description.
To explain the function and operation of the CPU in detail, consider the
example computer design in Figure 9.1. The CPU contains a general-purpose
data register called the accumulator (AC) and the program counter (PC). The
arithmetic logic unit (ALU) is used for arithmetic and logical operations.
The fetch, decode, and execute cycle can be implemented in this computer
using the sequence of register transfer operations shown in Figure 9.6. The next
instruction is fetched from memory with the following register transfer
operations:
MAR = PC
Read Memory, MDR = Instruction value from memory
IR = MDR
PC = PC + 1
