Digital Signal Processing Reference
In-Depth Information
Assembly Language
Machine Language
LOAD B
0211
ADD
C
0012
S T
R
E A
0 1 1 0
Figure 9.4
Example Computer Program for A = B + C.
The assignment of the data addresses must not conflict with instruction
addresses. Normally, the data is stored in memory after all of the instructions in
the program. In this case, if we assume the program starts at address 0, the
three instructions will use memory addresses 0,1, and 2.
The instructions in this example program all perform data operations and
execute in strictly sequential order. Instructions such as JUMP and JNEG are
used to transfer control to a different address. Jump and Branch instructions do
not execute in sequential order. Jump and Branch instructions must be used to
implement control structures such as an IF…THEN statement or program
loops. Details are provided in an exercise at the end of this section.
Assemblers are computer programs that automatically convert the symbolic
assembly language program into the binary machine language. Compilers are
programs that automatically translate higher-level languages, such as C or
Pascal, into a sequence of machine instructions. Many compilers also have an
option to output assembly language to aid in debugging.
The programmer's view of the computer only includes the registers (such as the
program counter) and details that are required to understand the function of
assembly or machine language instructions. Other registers and control
hardware, such as the instruction register (IR), memory address register
(MAR), and memory data register (MDR), are internal to the CPU and are not
described in the assembly language level model of the computer. Computer
engineers designing the processor must understand the function and operation
of these internal registers and additional control hardware.
9.2 The Processor Fetch, Decode and Execute Cycle
The processor reads or fetches an instruction from memory, decodes the
instruction to determine what operations are required, and then executes the
instruction as seen in Figure 9.5. A simple state machine called the control unit
controls this sequence of operations in the processor. The fetch, decode, and
execute cycle is found in machines ranging from microprocessor-based PCs to
supercomputers. Implementation of the fetch, decode, and execute cycle
requires several register transfer operations and clock cycles in this example
design.
The program counter contains the address of the current instruction. Normally,
to fetch the next instruction from memory the processor must increment the
program counter (PC). The processor must then send the address value in the
PC to memory over the bus by loading the memory address register (MAR) and
start a memory read operation on the bus. After a small delay, the instruction
