Digital Signal Processing Reference
In-Depth Information
Another version of the train.VHD program, dcc_train.zip is available on the
book's DVD that will control a DCC train setup. It replaces the video train
simulation module and produces the outputs needed to run the real DCC train
system. It contains a DCC IP core, DCC_low_level.vhd, which generates the
appropriate DCC signal packets as seen in Figure 8.13. The DCC data stream is
generated by combining the Speed switch inputs and the Train direction signals
(i.e., DA, DB) from the Tcontrol module. The appropriate DCC command
packet is created from these signals and then saved in a register. The registered
command is shifted out to produce a serial bit stream. The DCC standard only
provides for one-way communication, and thus, no transmission guarantee can
be made (i.e., no acknowledgement is sent back by the train). Therefore, a
given DCC command is repeatedly shifted out until another command is
received to ensure transmission of each command. Continuous transmission
also insures a consistent power level on the tracks.
Additional construction details for anyone building the FPGA-based DCC
model train setup are available at the topic's website. The FPGA uses five input
pins to read in from the IR photointerrupter track sensors, two output bits to
send DCC commands, and two output bits to control each of the three track
switches. Each track switch has two solenoid drivers that open and close a
switch. The proper solenoid must be briefly turned on or pulsed to move the
switch and then turned off. Leaving the solenoid turned on continuously will
overheat and eventually burn out the solenoid. The 50ms timed pulse required
to briefly energize a track switch's solenoid is already provided in the IP core.
To connect the train setup to all of the FPGA I/O pins, a ribbon cable can be
attached to one of the I/O expansion headers on the FPGA board with the other
end attached to the train interface circuitry on a protoboard or custom printed
circuit board (PCB). The FPGA device type and I/O pin assignments for the
train.VHD project will need to be changed depending on each user's custom
train interface circuitry and the FPGA board I/O expansion connector used.
Consult each FPGA board's reference manual for complete details on the I/O
expansion header's FPGA pin numbers.
8.13 Laboratory Exercises
1.
Assuming that train A now runs clockwise and B remains counterclockwise, draw a new
state diagram and implement the new controller. If you use VHDL to design the new
controller, you can modify the code presented in section 8.7. Simulate the controller and
then run the video train simulation.
2.
Design a state machine to operate the two trains avoiding collisions but minimizing their
idle time. Trains must not crash by moving the wrong direction into an open switch.
Develop a simulation to verify your state machine is operating correctly before running
the video train system. The trains are assumed to be in the initial positions as shown in
Figure 8.14. Train A is to move counterclockwise around the outside track until it comes
to Sensor 1, then move to the inside track stopping at Sensor 5 and waiting for B to pass
Sensor 3 twice. Trains can move at different speeds, so no assumption should be made
