State Machine Design: The Electric Train Controller - Rapid Prototyping of Digital Systems - page 158

// This code describes how the state machine operates

// This section will need changes for a different state machine

// State assignments are needed in Verilog

parameter ABout = 0, Ain = 1, Bin = 2, Astop = 3, Bstop = 4;

// This section describes how the state machine behaves

// this process runs once every time reset or the clock changes

always @( posedge clock or posedge reset)

begin

// Reset to this state (i.e. asynchronous reset)

if (reset)

state = ABout;

else

// posedge clock means positive clock edge

//This section will execute once on each positive clock edge

//Signal assignments in this section will generate D flip-flops

case (state) // Case statement to determine next state

A B o u t :

// This Case checks both sensor1 and sensor2 bits

case (sensor12)

2'b 00: state = ABout;

2'b 01: state = Bin;

2'b 10: state = Ain;

2'b 11: state = Ain;

// Default case is needed here

default : state = ABout;

endcase

A i n :

case (sensor24)

2'b 00: state = Ain;

2'b 01: state = ABout;

2'b 10: state = Bstop;

2'b 11: state = ABout;

default : state = ABout;

endcase

B i n :

case (sensor13)

2'b 00: state = Bin;

2'b 01: state = ABout;

2'b 10: state = Astop;

2'b 11: state = ABout;

default : state = ABout;

endcase

A s t o p :

if (sensor3)

s t a t e = A i n ;

else

s t a t e = A s t o p ;

Bstop:

if (sensor4)

s t a t e = B i n ;

else

s t a t e = B s t o p ;