Digital Signal Processing Reference
In-Depth Information
-- Outputs that depend on state, use state to select value
-- Be sure to specify every output for every state
-- values will not default to zero!
WITH
state
SELECT
Switch1 <=
'0'
WHEN
ABout,
'0'
WHEN
Ain,
'1'
WHEN
Bin,
'1'
WHEN
Astop,
'0'
WHEN
Bstop;
WITH
state
SELECT
Switch2 <=
'0'
WHEN
ABout,
'0'
WHEN
Ain,
'1'
WHEN
Bin,
'1'
WHEN
Astop,
'0'
WHEN
Bstop;
WITH
state
SELECT
DirA
<=
"01"
WHEN
ABout,
"01"
WHEN
Ain,
"01"
WHEN
Bin,
"00"
WHEN
Astop,
"01"
WHEN
Bstop;
WITH
state
SELECT
DirB
<=
"01"
WHEN
ABout,
"01"
WHEN
Ain,
"01"
WHEN
Bin,
"01"
WHEN
Astop,
"00"
WHEN
Bstop;
END
a;
8.7 Verilog Based Example Controller Design
The corresponding Verilog code for the state machine in Figures 8.5 and 8.6 is
shown below. A CASE statement based on the current state examines the inputs
to select the next state. At each clock edge, the next state becomes the current
state. A second CASE statement at the end of the program specifies the outputs
for each state. For additional Verilog help, see the help files in the Altera CAD
tools or look at the Verilog examples in Chapter 7.
// Example Verilog State machine to control trains
module
Tcontrol (reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5,
switch1, switch2, switch3, dirA, dirB);
// This section defines state machine inputs and outputs
// No modifications should be needed in this section
input
reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5;
output
switch1, switch2, switch3;
output
[1:0] dirA, dirB;
reg
switch1, switch2;
// dirA and dirB are 2-bit logic vectors(i.e. an array of 2 bits)
reg
[1:0] dirA, dirB;
reg
[2:0] state;
