Digital Signal Processing Reference
In-Depth Information
Sw3
A
T1
B
T3
S5
S1
S2
S3
S4
T4
T2
Sw1
Sw2
ABout:
DA0, DB0 ( DA = 1, DB = 1 )
Sw3
Sw3
A
T1
T1
B
T3
T3
S5
S5
S1
S2
S3
S4
S1
S2
S3
S4
T4
T4
A
B
B
T2
T2
Sw1
Sw2
Sw1
Sw2
Ain:
DA0, DB0 ( DA = 1, DB = 1 )
Bin:
DA0, DB0, Sw1, Sw2
( DA = 1, DB = 1, Sw1, Sw2 )
Sw3
Sw3
T1
T1
T3
T3
S5
S5
B
A
S1
S2
S3
S4
S1
S2
S3
S4
T4
T4
A
B
T2
T2
Sw1
Sw2
Sw1
Sw2
Bstop:
DA0 ( DA = 1, DB = 0 )
Astop:
DB0, Sw1, Sw2
( DA = 0. DB = 1, Sw1, Sw2 )
Figure 8.7
Working diagrams of train positions for each state.
Table 8.1 Outputs corresponding to states.
State
ABout
Ain
Astop
Bin
Bstop
Sw1
0
0
1
1
0
Sw2
0
0
1
1
0
Sw3
0
0
0
0
0
DA(10)
01
01
00
01
01
DB(10)
01
01
01
01
00
8.6 VHDL Based Example Controller Design
The corresponding VHDL code for the state machine in Figures 8.5 and 8.6 is
shown below. A CASE statement based on the current state examines the inputs
to select the next state. At each clock edge, the next state becomes the current
state. WITH…SELECT statements at the end of the program specify the
