Using VHDL for Synthesis of Digital Hardware - Rapid Prototyping of Digital Systems - page 127

Opcode Operation Function

000XX ALU_OUT <= A Pass A

001XX ALU_OUT <= A + B Add

010XX ALU_OUT <= AB Subtract

011XX ALU_OUT <= A AND B Logical AND

100XX ALU_OUT <= A OR B Logical OR

101XX ALU_OUT <= A + 1 Increment A

110XX ALU_OUT <= A1 Decrement A

111XX ALU_OUT <= B Pass B

XXX00 Y <= ALU_OUT Pass ALU_OUT

XXX01 Y<= SHL(ALU_OUT) Shift Left

XXX10 Y<=SHR(ALU_OUT) Shift Right (unsignedzero fill)

XXX11 Y<= 0 Pass 0's

4. Use the Cyclone chip as the target device. Determine the worst case time delay of the
ALU using the timing analyzer. Examine the report file and find the device utilization.
Use the logic element (LE) device utilization percentage found in the compilation report
to compare the size of the designs.
5. Explore different synthesis options for the ALU from problem 3. Change the area and
speed synthesis settings in the compiler under Assignments Settings Analysis and
Synthesis Settings , rerun the timing analyzer to determine speed, and examine the report
file for hardware size estimates. Include data points for the default, optimized for speed,
balanced, and optimized for area settings. Build a plot showing the speed versus area
trade-offs possible in the synthesis tool. Use the logic element (LE) device utilization
percentage found in the compilation report to compare the size of the designs.
6. Develop a VHDL model of one of the TTL chips listed below. The model should be
functionally equivalent, but there will be timing differences. Compare the timing
differences between the VHDL FPGA implementation and the TTL chip. Use a data
book or find a data sheet using the World Wide Web.
A. 7400 Quad nand gate
B. 74LS241 Octal buffer with tri-state output
C. 74LS273 Octal D flip-flop with Clear
D. 74163 4-bit binary counter
E. 74LS181 4-bit ALU
7. Replace the 8count block used in the tutorial in Chapter 4, with a new counter module
written in VHDL. Simulate the design and download a test program to the UP3 board.
8. Implement a 128 by 32 RAM using VHDL and the Altsyncram function. Do not use
registered output options. Target the design to the Cyclone EP1C6240C8 device. Use the
timing analyzer to determine the worst-case read and write access times for the memory.
9. Study the VHDL code in the LCD Display FPGAcore function and draw a state diagram
of the initialization and data transfer operations and explain its operation. You may find it
helpful to examine the data sheet for the LCD display's microcontroller.