Using VHDL for Synthesis of Digital Hardware - Rapid Prototyping of Digital Systems - page 124

debounce onepulse

PB1 PB1_Debounced PB1_Single_Pulse

pb
clock_100Hz

pb_debounced PB_debounced

clock

PB_single_pulse

inst1 Clock_1Mhz inst2

Clock_100Hz

clk_div

Clock_48Mhz

clock_48Mhz clock_1MHz

clock_100KHz
clock_10KHz
clock_1KHz
clock_100Hz
clock_10Hz
clock_1Hz

inst

Figure 6.2 Schematic of Hierarchical Design Example

LIBRARY IEEE ;
USE IEEE . STD_LOGIC_1164 . ALL ;
USE IEEE .STD_LOGIC_ARITH. ALL ;
USE IEEE .STD_LOGIC_UNSIGNED. ALL ;
ENTITY hierarch IS

PORT ( clock_48MHz, pb1 : IN STD_LOGIC ;

pb1_single_pulse : OUT STD_LOGIC );

END hierarch;
ARCHITECTURE structural OF hierarch IS
-- Declare internal signals needed to connect submodules
SIGNAL clock_1MHz, clock_100Hz, pb1_debounced : STD_LOGIC ;
-- Use Components to Define Submodules and Parameters

COMPONENT debounce

PORT ( pb, clock_100Hz : IN STD_LOGIC ;

pb_debounced : OUT STD_LOGIC );

END COMPONENT ;

COMPONENT onepulse

PORT (pb_debounced, clock : IN STD_LOGIC ;

pb_single_pulse : OUT STD_LOGIC );

END COMPONENT ;

COMPONENT clk_div

PORT ( clock_48MHz : IN STD_LOGIC ;

clock_1MHz : OUT STD_LOGIC ;

clock_100kHz : OUT STD_LOGIC ;

clock_10kHz : OUT STD_LOGIC ;

clock_1kHz : OUT STD_LOGIC ;

clock_100Hz : OUT STD_LOGIC ;

clock_10Hz : OUT STD_LOGIC ;

clock_1Hz : OUT STD_LOGIC );

END COMPONENT ;

BEGIN