Digital Signal Processing Reference
In-Depth Information
On the Cyclone FPGA chip, the memory can be implemented using the M4K
memory blocks, which are separate from the FPGA's logic cells. In the Cyclone
EP1C6 chip there are 20 M4K RAM blocks at 4Kbits each for a total of 92,160
bits. In the Cyclone EP1C12 there are 52 M4K blocks for a total of 239,616
bits. Each M4K block can be setup to be 4K by 1, 2K by 2, 1K by 4, 512 by 8,
256 by 16, 256 by 18, 128 by 32 or 128 by 36 bits wide. The
Tools MegaWizard
Plug-in Manager
feature is useful to configure the
Altsyncram parameters.
6.15 Hierarchy in VHDL Synthesis Models
Large VHDL models should be split into a hierarchy using a top-level structural
model in VHDL or by using the symbol and graphic editor in the Quartus II
tool. In the graphical editor, a VHDL file can be used to define the contents of a
symbol block. Synthesis tools run faster using a hierarchy on large models and
it is easier to write, understand, and maintain a large design when it is broken
up into smaller modules.
An example of a hierarchical design with three submodules is seen in the
schematic in Figure 6.2. Following the schematic, the same design using a top-
level VHDL structural model is shown. This VHDL structural model provides
the same connection information as the schematic seen in Figure 6.2.
Debounce, Onepulse, and Clk_div are the names of the VHDL submodules.
Each one of these submodules has a separate VHDL source file. In the Quartus
II tool, compiling the top-level module will automatically compile the lower-
level modules.
In the example, VHDL structural-model example, note the use of a component
declaration for each submodule. The component statement declares the module
name and the inputs and outputs of the module. Internal signal names used for
interconnections of components must also be declared at the beginning of the
component list.
In the final section, port mappings are used to specify the module or component
interconnections. Port names and their order must be the same in the VHDL
submodule file, the component instantiations, and the port mappings.
Component instantiations are given unique labels so that a single component
can be used several times.
Note that node names in the schematic or signals in VHDL used to interconnect
modules need not always have the same names as the signals in the components
they connect. Just like signal or wire names in a schematic are not always the
same as the pin names on chips that they connect. As an example,
pb_debounced on the debounce component connects to an internal signal with a
different name, pb1_debounced.
