Digital Signal Processing Reference
In-Depth Information
Inside a process, statements are executed in sequential order, and all processes
are executed in parallel. If multiple assignments are made to a signal inside a
process, the last assignment is taken as the new signal value.
A
A
B
C
B
C
X
Y
D(1)
D(2)
D(1)
D(2)
LIBRARY
IEEE
;
-- Include Libraries for standard logic data types
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
-- Entity name normally the same as file name
ENTITY
gate_network
IS
-- Ports: Declares module inputs and outputs
PORT
( A, B, C :
IN
STD_LOGIC
;
-- Standard Logic Vector ( Array of 4 Bits )
D
:
IN
STD_LOGIC_VECTOR
( 3
DOWNTO
0 );
-- Output Signals
X, Y
:
OUT
STD_LOGIC
) ;
END
gate_network;
-- Defines internal module architecture
ARCHITECTURE
behavior
OF
gate_network
IS
BEGIN
-- Concurrent assignment statements operate in parallel
-- D(1) selects bit 1 of standard logic vector D
X <= A
AND
NOT
( B
OR
C )
AND
( D( 1 )
XOR
D( 2 ) );
-- Process must declare a sensitivity list,
-- In this case it is ( A, B, C, D )
List includes all signals that can change the outputs
PROCESS
( A, B, C, D )
BEGIN
Statements inside process execute sequentially
Y <= A
AND
NOT
( B
OR
C)
AND
( D( 1)
XOR
D( 2 ) );
END
PROCESS
;
END
behavior;
6.5 VHDL Synthesis Model of a Seven-segment LED Decoder
The following VHDL code implements a seven-segment decoder for seven-
segment LED displays. A 7-bit standard logic vector is used to assign the value
of all seven bits in a single case statement. In the logic vector, the most-
significant bit is segment 'a' and the least-significant bit is segment 'g'. The
logic synthesis CAD tool automatically minimizes the logic required for
implementation. The signal MSD contains the 4-bit binary value to be
