Digital Signal Processing Reference
In-Depth Information
5.5 FPGAcore Clk_Div: Clock Divider
clk_div
clock_48Mhz
clock_1MHz
clock_100KHz
clock_1MHz
clock_100KHz
clock_10KHz
clock_10KHz
clock_1KHz
clock_1KHz
clock_100Hz
clock_100Hz
clock_10Hz
clock_10Hz
clock_1Hz
clock_1Hz
inst
Figure 5.5
Symbol for Clk_Div FPGAcore.
The FPGAcore Clk_Div shown in Figure 5.5 is used to provide clock signals
slower than the on-board clock oscillator. The output signals are obtained by
dividing down the clock input signal. Multiple output taps provide clock
frequencies in powers of ten.
5.5.1 VHDL Component Declaration
COMPONENT
clk_div
PORT
(
clock_48MHz
:
IN
STD_LOGIC
;
clock_1MHz
:
OUT
STD_LOGIC
;
clock_100kHz
:
OUT
STD_LOGIC
;
clock_10kHz
:
OUT
STD_LOGIC
;
clock_1kHz
:
OUT
STD_LOGIC
;
clock_100Hz
:
OUT
STD_LOGIC
;
clock_10Hz
:
OUT
STD_LOGIC
;
clock_1Hz
:
OUT
STD_LOGIC
);
END
COMPONENT
;
5.5.2 Inputs
A different frequency input clock is used on different FPGA boards, so each
board has a slightly different version of this function. The UP3 version is
shown. Clock_48MHz is an input pin that should be connected to the UP3 on-
board 48MHz USB clock. The pin number for the UP3's 48MHz USB clock is
29. Make sure the JP3 jumper selects the 48MHz USB clock (default setting).
5.5.3 Outputs
Clock_1MHz through clock_1Hz provide output signals of the specified
frequency. Based on a crystal oscillator, the actual frequency is 1.007 ± .005%
times the listed value.
Table 5.5 The Crystal Oscillator Clock Pin Assignments
Pin
Name
Function
of Pin
DE1
DE2
UP3
UP2, UP1
Pin Type
2550MHz
Clock
CLOCK
L1 50Mhz
N2 50Mhz
153 48Mhz
91 25Mhz
Input
