Digital Signal Processing Reference
In-Depth Information
5.4 FPGAcore OnePulse: Pushbutton Single Pulse
onepulse
PB_debounced
PB_debounced
clock
PB_single_pulse
clock
inst
Figure 5.4
Symbol for OnePulse FPGAcore.
The FPGAcore OnePulse shown in Figure 5.4 is a pushbutton single-pulse
circuit. Output from the pushbutton is High for only one clock cycle no matter
how long the pushbutton is pressed. This function is useful in state machines
that read external pushbutton inputs. In general, fewer states are required when
it is known that inputs only activate for one clock cycle. Internally, an edge-
triggered flip-flop is used to build a simple state machine.
5.4.1 VHDL Component Declaration
COMPONENT
onepulse
PORT
( PB_debounced, clock :
IN
STD_LOGIC
;
PB_single_pulse
:
OUT STD_LOGIC
);
END
COMPONENT
;
5.4.2 Inputs
PB_debounced is the debounced pushbutton input. It should be connected to a
debounced pushbutton.
Clock is the user's state-machine clock. It can be any frequency. In some
designs, the user may want to edit the VHDL code to add a reset input.
5.4.3 Outputs
PB_single_pulse is the output, which is High for only one clock cycle when a
pushbutton is hit.
