ECG Acquisition in a Computer - ECG Acquisition and Automated Remote Processing - page 78

w

Equivalent BPE output bit pattern

w

Input data bit stream

0 0 0 1 0 1 1 0

Fig. 4.2 Bi-phase modulation principle illustrated

output, which may occur due to successive '0' or '1' bits, is avoided, instead a
continuous time varying signal is generated at the output of the encoder device.

4.3.2 Standalone Embedded Systems for ECG Encoding
and Decoding

As already mentioned, there are two standalone systems, viz., PTK and HES which
are placed at the two ends of the transmission link [ 28 ]. The PTK consists of
analog signal conditioning modules, a single channel AD converter, Atmel 89C51
MCU, 32 kB SRAM for onboard buffering of ECG samples and driving circuit for
transmitter. The analog signal conditioning block consists of a low-offset instru-
mentation amplifier (INA) followed by a DC shifting arrangement to make the
amplified output unipolar and hence compatible with the input of ADC 0804,
which is driven at free-running mode. The block schematic of the PTK is shown is
Fig. 4.3 . The sampling frequency of the AD converter is set as 1 kHz. The PTK
collects the ECG samples and continuously fills-up the buffer. After the data are
stored, the MCU prepares the data packets and error codes for generating the byte-
stream to the transmitter unit. Designing the packet stream is done keeping in view
of simplicity, ease in implementation and decoding. Each packet is constituted by
a one fixed header, one byte packet number, 32 encoded data bytes, and one error
checking code. A fixed header (255 10 ) is used for synchronization between the
transceiver units. The packet number is used for BER and PE computation. A
typical packet format is shown in Fig. 4.4 . For the present case, a simple modular
checksum principle is used. The algorithm for generating one encoded packet is
given in end of Chapter Appendix 1 . Each encoded byte is further formatted with a
'LOW' start bit, 8 data bits and a 'HIGH' stop bit to form the data frame. Precise
bit width in the MCU is generated by using two dedicated delay subroutines, each
for bit '1' and bit '0'. The output bit line of the MCU is complemented at the end
of respective delays which are executed as per the bit's status of a particular frame.
HES receives the demodulated output from the receiver unit and decodes then
real time to extract the data frames, then transfers the data bytes to the standalone
computer using RS-232 protocol. The block schematic of HES unit is shown in
Fig. 4.5 [ 29 ]. The output of the receiver is in sinusoidal form, and hence, a wave
shaping circuit is used for converting it into an equivalent binary bit stream which