ECG Acquisition in a Computer - ECG Acquisition and Automated Remote Processing - page 79

Driving
circuit for
Wireless
Transmitter

Transmitter
unit of the
communication
module

Instrumentation
Amplifier
+
Level shifter

Single
channel
AD
Converter

MCU

ECG source

Static RAM

PES

PES

Fig. 4.3 Block schematic of the PTK

Header Packet

number

Encoded data bytes (1-32) Checksum byte

'sync
pattern'

Fig. 4.4 Structure of a transmitted 35-byte packet from PES

is delivered to the MCU (Atmel 89C2051). The decoding of input data stream is
performed by accurate computation of the bit intervals between successive state
transitions using the timer elements of the MCU. The timer element compares this
bit interval value with a reference level and the decoded bit status is assigned. A
'0' bit is encoded from one wider pulse and '1' bit from two consecutive thinner
pulses. The algorithm flowchart of this decoding is given in end of Chapter
Appendix 2 .
Initially, the HES MCU looks for a match of the 'header' pattern from the
decoded frames, and when it is found, it accepts the subsequent bytes for further
processing. For each decoded frame, the start and stop bits are selectively dis-
carded to extract the data byte only in the following manner. From the point of
matching, the last 8 bits out of 10 (a complete frame) are accepted for all suc-
cessive decoded data frames. This automatically discards the stop bit of preceding
frame and start bit of the following frame, as indicated in Fig. 4.6 . The next
function is to modify the decoded packets for BER and PE estimation. For this, a

DAC ECG signal output

Receiver unit
of the
communication
module

Wave-
Shaping
circuit

MAX 232
level
converter

MCU

RS-232
communication

PC with GUI
based data
processing
software

D-connector

HES

Fig. 4.5 Block schematic of the HES module