The end of Moore’s law - The Computing Universe: A Journey through a Revolution - page 301

2018, and long-term goals, 2019 through 2026. On the near-term goal, the ITRS
comments:

Scaling planar CMOS [complementary metal oxide silicon, the technology
used to build integrated circuits] will face significant challenges. The
conventional path of scaling, which was accomplished by reducing the
gate dielectric thickness, reducing the gate length, and increasing the
channel doping, might no longer meet the application requirements set by
performance and power consumption. Introduction of new material systems
as well as new device architectures, in addition to continuous process control
improvement are needed to break the scaling barriers. 7
On the longer-term outlook, the ITRS report highlights the problem of manag-
ing the power leakage of CMOS devices:

Fig. 15.7. Eric Dexler's vision of nano-
technology included fabricating such
things as molecular differential gears.

While power consumption is an urgent challenge, its leakage or static
component will become a major industry crisis in the long term, threatening
the survival of CMOS technology itself, just as bipolar technology was
threatened and eventually disposed of decades ago. Leakage power varies
exponentially with key process parameters such as gate length, oxide
thickness, and threshold voltage. This presents severe challenges in light of
both technology scaling and variability. Off-currents in low-power devices
increase by a factor of 10 per generation, and will emphasize a combination
of drain and gate leakage components. Therefore design technology must
be the key contributor to maintain constant or at least manageable static
power. 8

In May 2011, Intel announced the most radical shift in semiconductor technol-
ogy in fifty years. The new Intel technology uses the latest fabrication process
to produce three-dimensional transistors that allow microprocessors to oper-
ate faster and use less power than conventional two-dimensional transistors.
According to Moore:

For years we have seen limits to how small transistors can get. This
change in the basic structure is a truly revolutionary approach,
and one that should allow Moore's Law, and the historic pace of
innovation, to continue. 9
Research that led to this breakthrough started in 1997, in a
DARPA-funded project at the University of California, Berkeley.
The Berkeley team ( B.15.3 ), Chenming Hu, Jeff Bokor, and Tsu-Jae
King Liu, looked at the challenge of building a transistor smaller
than twenty-five nanometers, ten times smaller than those in
production at the time. (A nanometer is a thousand-millionth of a
meter.) Two years later, the researchers came up with the idea of a
new three-dimensional transistor structure they called a “FinFET”
( Fig. 15.8 ). This is a field effect transistor (FET) formed with a narrow
silicon “fin” rising from the surface of the chip. A FET operates
by creating an electric field that changes how one of the tran-
sistor's semiconductor regions, the gate region, conducts electric
current. In a standard two-dimensional FET, the current can only
be controlled from the top surface of a silicon channel linking the

B.15.3. The FinFET transistor team at Berkeley.
From left to right: Ali Javey, Vivek Subramanian,
Ali Niknejad, Jeff Bokor, Chenming Hu, and Tsu-
Jae King Liu.