Environmental Engineering Reference
In-Depth Information
Figure 4.8
A schematic diagram of the glass/CG(metal-1)/CdS/CdTe/
metal-2devicestructureaccordingtothenewunderstanding(nottoscale).
the energy band diagram of the device according to the new un-
derstanding takes the form shown in Figs. 4.8 and 4.9, respectively.
In these devices, the CdS layer is n-type and usually provides a
bettersubstratethantheconductingglassforgrowthofhigh-quality
CdTe material. During the annealing process, the intermixing of
CdS and CdTe takes place, forming CdS
x
Te
1
−
x
ternary compounds,
creatingagradedbandgapinterfaceatthehetero-junction.Chemical
treatments and the annealing process improve the crystallinity of
the semiconducting layers, form larger grains, remove unwanted
defects in the material, passivate grain boundaries, and bring the
doping concentrations to moderate values in the range mid-10
14
to
mid-10
17
cm
−
3
. The bulk of the CdTe layer remains n-type during
processing, and the outermost layer contains high concentrations
of defects responsible for Fermi-level pinning at one of the five
experimentally identified levels. The thickness of the top surface
layer varies in the region of a few 100 A, depending on the
processing steps such as the heat treatment and etching procedure.
If the Fermi level is pinned close to the valence band, at 0.96
±
0.04
or 1.18
±
0.02 eV below the conduction band minimum, a large
Schottky barrier is formed at the metal/CdTe interface, creating the
required band bending across the device for PV activity. Then, the
top surface layer of the CdTe material can be considered a p-type
layer since the Fermi level is close to the valence band maximum.
