Models for Bridging Defects Test and Diagnosis - Models in Hardware Testing - page 37

that V A is properly interpreted by NAND3 (R C.NAND3/ ), and for a higher resistance
V B is also properly interpreted by NAND4 (R C.NAND4/ ). Therefore:
When R b <R C.NAND3/ , logic errors are propagated through both NAND3 and
NAND4 .
When R C.NAND3/ <R b <R C.NAND4/ , logic errors are propagated through
NAND4 .
When R b >R C.NAND4/ , the circuit does not show faulty logic behaviour.
For a given resistive bridging defect, the proposed model allows to easily compute
during fault simulation, the different critical resistances (R C.NAND3/ , R C.NAND4/ /
which, in fact, define the range of detectable resistance associated to the defect. This
information is used during fault simulation to evaluate some quality metrics of the
test vectors. The first model proposed in 1996 used simplified transistor equations.
In a more recent work carried out by Polian et al. ( 2005 ), the critical resistance was
calculated based on more accurate transistor models: the Fitted Model, which uses
equations with free variables that are fitted in order to match actual SPICE data, and
the Predictive Model, which is fully analytical and employs BSIM4 equations.
Finally, an analysis of the behaviour of bridging defects was presented by
Sar-Dessai and Walker ( 1999 ). This work analysed five different bridging fault con-
figurations, namely: a bridging fault between two primary inputs, between a primary
input and a gate output, between two gate outputs, between two gates outputs driv-
ing the same gate and between two primary outputs. Based on the model for these
five configurations, look-up tables can be constructed, where the information about
the voltage on the bridged nets is stored for every vector. The detectable resistance
interval and the propagating path are also taken into account. Furthermore, it is also
determined whether the bridging fault is detectable at the driven gate outputs based
on their logic thresholds.

2.2.4 Modeling Feedback Bridging Faults

A feedback bridging fault is a bridging fault such that both involved nets lie on the
same path in the circuit ( Mei 1974 ). The voltage value of one bridged net may de-
pend on the value of the other bridged net. The bridged net with lower topological
ordering is usually called the back net, while the other one is called the front net.
The analysis of feedback bridging faults is complex. They can induce sequential
behaviour in combinational circuits, depending whether the path is sensitized or not
and depending also on the topological situation of the bridge. Thus, three differ-
ent cases may appear ( Rajsuman 1991 ; Koch and Muller-Glaser 1993 ; Chess and
Larrabee 1998 ; Dahlgren 1988 ):
1. The logic path is not sensitized.
2. The logic path is sensitized and the feedback loop has an even number of
inversions.
3. The logic path is sensitized and the feedback loop has an odd number of
inversions.