Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 212

reflecting as much as possible the real defects and faults that are likely to af-
fect both the production and the operational phases. Hardware testing was initially
based on the assumption that defects could be adequately modeled by stuck-at-0
and stuck-at-1 logical faults associated with the logic diagram of the circuit un-
der test. Nevertheless, with the increasing integration density, this hypothesis has
become less and less sound. Similar concerns about fault representativeness apply
to the definition of suitable fault tolerance mechanisms (error detection and recov-
ery) meant to cope with faults occurring during normal operation (on-line testing).
Fault representativeness issues also impact the specific testing methods (classically,
fault injection techniques), that are specifically intended to assess the fault tolerance
mechanisms against the typical sets of inputs they are a meant to cope with: the
faults and errors induced. Such techniques are to be related to the simulation tech-
niques described in Chapter 4 for estimating the quality of test sets, with respect to
manufacturing defects.
This chapter addresses fault representativeness issues at large, i.e., encompass-
ing the definition and application of various forms of testing: off-line testing with
respect to manufacturing defects and on-line testing mechanisms to cope with faults
occurring during normal operation (Section 8.2 ) , and a recursive form of testing
designed to assess the coverage of the fault tolerance mechanisms (Section 8.3 ) .
Finally, Section 8.4 concludes the chapter.
It is worth noting that the results reported in Section 8.2 are based on seminal
research work carried out at LAAS-CNRS during years 1975-1980 and directed
by Christian Landrault (first work by Christian devoted to hardware testing). These
studies were dedicated to the design of easily testable and self-checking LSI circuits.
We voluntarily maintained the historical and pioneering perspective of that work in
keeping the original figures, among which some are from Christian's hand.
Before moving to the next section of this chapter, we will provide here some basic
definitions and terminology about hardware dependability issues that will be used
throughout the paper, and that are compliant with the currently widely accepted
taxonomy in the domain ( Avi zienis et al. 2004 ). In this process, we assume the
recursive nature attached to the notions of failure , faul t , error , failure , fault ,etc.:
a. Defect : a physical defect is a failure occurring in the manufacturing process or
in operation (e.g., short, open, threshold voltage drift, etc.).
b. Fault : a fault is the direct consequence of a defect. At the logical level, the most
popular fault model has been for long time the stuck-at-X fault model - X 2
f 0, 1 g . A defect is equivalent to a stuck-at X of a line l (l=X/ if the behavior of
the defective circuit is identical to the behavior of a perfect circuit with the line
maintained at logical value X .
c. Error : an error corresponds to the activation of a fault that induces an incorrect
operation of the target system (IC or system including the IC). A line presents an
error at a value X if, during normal operation, it is at the logical value X instead
of the value X . The error observed at a given point of a target IC, depends not
only on the type of fault, but also on the structure of the circuit (logical function),
as well as the logical inputs and outputs of the circuit. A defect may induce: