Hardware Reference
In-Depth Information
A single error, if it only influences one output
A unidirectional error, if it impacts several outputs in the same manner
A multiple error, if it influences several outputs in different ways
d.
Failure
: A failure occurs when the service delivered by the target system is per-
ceived by its users as deviating from the correct one. This has to be related to
the definition that illustrates the recursion attached to the concepts governing the
fault-error-failure pathology.
8.2
Fault Models and Off-Line/On-Line Testing
Off-line and on-line testing techniques have been based for long time on the as-
sumption that defects may be modeled by stuck-at-0 and stuck-at-1 logical faults
associated with the logic diagram of the circuit to be tested. This hypothesis is be-
coming less and less sound with the advance of integration technology. This section
Section
8.2.1
derives a set of fault assumptions motivated by the physical origin
of the defects observed by direct inspection of 4-bit microprocessor chips. A great
majority of the defects affecting complex gates are shorts and opens that cannot be
accounted for by the commonly used logic level models. Section
8.2.2
deals with
the generation of
(off-line) test sequences
for such defects. Section
8.2.3
proposes
layout rules aimed at facilitating testing procedures. These rules aim at decreasing
the variety of possible defects and at avoiding those that are not easily testable. By
adhering to these rules, then logic level models are again able to accurately represent
problem of designing fault-tolerant systems able to cope with defect manifestations
during operation. Proposals helping the design of circuits better adapted to the real-
ization of fault-tolerant systems (
Sedmak and Liebergot
1978
;
Rennels et al.
1978
)
are provided. These sections focus on
on-line testing
issues for detecting errors
induced by the physical defects in operation. Suitable error models and related im-
plementation rules aimed at facilitating the efficiency of the detection are briefly
presented. Finally, Section
8.2.6
provides concluding remarks.
8.2.1
Defects Analysis for MOS LSI
The problem of test generation can be formulated as follows: given a description of
the target circuit and a list of faults, derive the shortest sequence of input vectors
enabling the detection of the faults in the list. This detection must be ensured by
observing the primary outputs of the circuit, only. The nature of the considered list
of faults strongly influences the test sequence generation. The more these faults are
related to the physical nature of the circuit, the higher the quality of the test, but
