Models for Power-Aware Testing - Models in Hardware Testing - page 191

Fig. 7.7 Impact of elevated
peak power during test

High Instantaneous Current

Elevated Peak Power

Power Supply Noise (IR-Drop, Ldi/dt)

Significant Delay Increase due to Excessive PSN

Erroneous Behavior Only During Testing (test fail)

Manufacturing Yield Loss (Overkill)

are declared faulty) and hence manufacturing yield loss ( Butler et al. 2004 ). These
phenomena have been widely reported in the literature, in particular when at-speed
scan testing is performed ( Saxena et al. 2003 ).
In order to avoid excessive peak power consumption and its related issues, it is
important to reduce the level of switching activity during test. This can be done by
dedicated and efficient solutions as those described in the next sections.

7.4 Power-Aware Test Generation

Power-aware test generation can be used to create patterns that are inherently op-
timized to achieve minimum switching activity. In this section, we first provide an
overview of power-aware test pattern based approaches. The description will be
limited to approaches where test patterns are generated by an ATPG tool and target
scan-based designs. Next, we describe a solution for low energy Built-In Self-Test
(BIST) where the parameters of the test generator are tuned to provide low switching
on-chip test patterns.

7.4.1 Overview of Power-Aware Test Generation Solutions

Power-aware test pattern generation for scan testing can be used for either shift
power reduction or capture power reduction. Solutions proposed so far can be cate-
gorized as described below.

7.4.1.1 Low-Power ATPG

Low-power ATPG consists in modifying an existing ATPG algorithm or developing
a new one for generating low-power test patterns that still meet the original ATPG