Models for Power-Aware Testing - Models in Hardware Testing - page 189

and permanent damage (referred to as infant mortality) of the circuit ( Pouya and
Crouch 2000 ) .
Reduced reliability . Another type of structural degradations, which are accel-
erated gradually over time (ageing), may affect circuit performance or cause
functional failures after a given lifetime ( Hertwig and Wunderlich 1998 ; Shi and
Kapur 2004 ) . In this case, the main mechanisms leading to these structural degra-
dations are corrosion, hot-carrier-induced defects, electro-migration or dielectric
breakdown ( Altet and Rubio 2002 ). The occurrence of these degradation mecha-
nisms will therefore affect long-term circuit reliability.
Yield loss . High switching activity during test may lead not only to elevated av-
erage power and hence temperature increase, but also to temperature variations
that may differ from those in functional mode. These temperature variations may
induce timing variations and in some cases may lead to yield loss (also called
overkill).

Besides the above circuit related issues, excessive average power during test may
also have the following impact on the test process, and hence on test cost (see
Fig. 7.5 ) :

Elevated Average Power

Temperature Increase

Excessive Heat Dissipation

Structural
degradations
(hot spots)

Hot-Carrier-Induced Defects
Electro-migration
Dielectric Breakdown

Temperature Variation
Timing Variations different
from functional mode

Chip Damage Reduced Reliability Yield Loss

Fig. 7.4 Impact of elevated average test power on the circuit

Elevated Average Power
(temperature increase, excessive heat dissipation)

Low Allowable Parallelism
(Wafer Testing & Package Testing)

Reduced Test Frequency

Low Test Throughput

Fig. 7.5 Impact of elevated average test power on the test process