Models for Power-Aware Testing - Models in Hardware Testing - page 188

weighted by their position in the scan chain are counted to provide a rough estimate
of test power. Though the correlation with the overall circuit test power is quite
good, a drawback of this metric however is that it does not provide an accurate value
of test power dissipation as it neglects combinational logic toggling. Nevertheless,
this metric remains an efficient mean to compare different solutions (DFT/ATPG)
in terms of test power dissipation.
In order to quickly power-analyze ATPG patterns and better define the final DFT
architecture, stochastic power estimation techniques based on using transition prob-
abilities at flip-flop outputs can be adopted ( Ravi et al. 2008 ). Alternatively, RT-level
test power estimators can be used but only if DFT insertion and test generation can
be done at the RT-level ( Midulla and Aktouf 2008 ) .

7.3 Overview of Power Issues During Test

Power issues during test application may occur when the circuit switching activity
is higher than the switching activity during functional mode of operation. In this
case, the circuit may be unable to behave properly as power constraints considered
during the design process have been violated. These power issues are mainly due to
two reasons: excessive average power consumption and excessive peak power con-
sumption during test. In this section, we explain the origins and the consequences
of these power issues during scan testing.

7.3.1 Issues due to Elevated Average Power

As explained in the previous section, the switching operations of a circuit always
lead to heat dissipation. The heat is produced by the collision of carriers with the
conductor molecular structure (Joule effect) and is responsible for die temperature
increase observed during operation. There is a well-known relationship between die
temperature and power dissipation that can be formulated as follows ( We s t e a n d
Eshraghian 1993 ):

T die D T air C ™ P Average (7.9)

Where T die is the die temperature, T air is the temperature of surrounding air, ™ is the
package thermal impedance expressed in ı C=Wa t t , a n d P Average is the average power
dissipated by the circuit.
From the above expression, it is clear that an increase of average power dissipa-
tion will increase the circuit temperature. If the temperature is too high, even during
the short duration of a manufacturing or on-line test session, it may have the follow-
ing impacts on the circuit (see Fig. 7.4 ) :

Chip damage . The excessive heat related to high temperature may lead to hot
spots, which appear during test data application and may result in premature