Models for Power-Aware Testing - Models in Hardware Testing - page 185

Fig. 7.2 Static leakage

power

Gate

Source

Drain

N+

N+

I SUB

I GATE I GIDL I RB

Psub

output. The dynamic switching power consumed by the logic gate during the time
interval Œ0; T can finally be expressed as:

P dyn D 1=2:C L :V DD :N:1=T (7.2)

The above analysis shows that dynamic switching power consumption occurs dur-
ing the charge of output capacitance, whereas power (or energy) dissipation occurs
during the charge or discharge of each node. Considering that average power is
given by the ratio between energy and time, it can be observed that the power dis-
sipated by N rising or falling transitions during the time interval Œ0; T is given by
E=T D 1=2:C L :V DD :N:1=T . This expression is equivalent to the above expression
of the dynamic switching power consumption. It can be concluded that the terms
“power consumption” and “power dissipation” can be used without distinction.
Static (or leakage) power is the power consumed when the circuit is idle and is
due to four main components (see Fig. 7.2 ) : the reverse-biased junction leakage cur-
rent .I RB /, the gate induced drain leakage current .I GIDL /, the gate direct-tunneling
leakage current .I GATE / and the sub-threshold leakage current .I SUB /. The latter is
the main contributor to static power dissipation and is proportional to the ratio be-
tween V DD and the threshold voltage of transistors inside the gate ( Roy et al. 2003 ) .

7.2.2 Test Power Modeling

In order to explain the dynamic switching power dissipation during test, let us con-
sider a circuit composed of N nodes and a test sequence of length L used to achieve
a given fault coverage ( Girard et al. 2007 ). The average energy consumed at node
i per switching is 1=2:C i :V DD 2 where C i is the equivalent output capacitance at
node i and V DD the power supply voltage ( Cirit 1987 ) . A good approximation of
the energy consumed at node i in a time interval t is 1=2:C i :S i :V DD where S i is
the average number of transitions during this interval (also called switching activ-
ity factor at node i ). Furthermore, nodes connected to more than one logic gate in
the circuit are nodes with a higher output capacitance. Based on this fact, and in a
first approximation, it can be stated that output capacitance C i is proportional to the
fanout at node i , denoted as F i ( Wang and Roy 1995 ). Therefore, an estimation of
the energy E i consumed at node i during the time interval t is given below, where
C 0 is the minimum output capacitance of the circuit.